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cyw20734 single-chip bluetooth transceiver for wireless input devices cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14874 rev. *s revised tuesday, october 4, 2016 the cypress cyw20734 is a bluetooth 4.1- compliant, stand-alone baseband processor wi th an integrated 2.4 ghz transceiver. manufactured using the industry's most advanced 40 nm cmos lo w-power process, the cyw20734 employs the highest level of integration to eliminate all critical exte rnal components, thereby minimizing the devic e's footprint and the costs associated w ith implementing bluetooth solutions. the cyw20734 is the optimal solution for applications in wir eless input devices including game controllers, remote, keyboards, and joysticks. built-in firmware adheres to the bluetooth low energy (ble) profile and the ble human interface device (hid) profile . cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. applications game controllers wireless pointing devices (mice) remote controls wireless keyboards joysticks home automation point-of-sale input devices 3d glasses blood pressure monitors ?find me? devices heart rate monitors proximity sensors thermometers features complies with bluetooth core specification version 4.1 including br/edr/ble ble hid profile version 1.00 compliant bluetooth device id profile version 1.3 compliant supports generic access profile (gap) supports adaptive frequency hopping (afh) excellent receiver sensitivity programmable output power control integrated arm cortex-m3 microprocessor core on-chip power-on reset (por) support for eeprom and serial flash interfaces integrated low dropout regulator (ldo) on-chip software controlled power management unit programmable key scan matrix in terface, up to 8 20 key- scanning matrix three-axis quadrature signal decoder pcm/i 2 s interface infrared modulator ir learning auxiliary adc with up to 28 analog channels one mono microphone input on-chip support for serial peripheral interface (master and slave modes) broadcom serial communications interface (compatible with nxp i 2 c slaves) package type: ? 90-pin fbga package (8.5 mm 8.5 mm) ? rohs compliant table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM20734 cyw20734 BCM20734ua1kffb3g cyw20734ua1kffb3g
document number: 002-14874 rev. *s page 2 of 51 cyw20734 figure 1. functional block diagram iot resources cypress provides a wealth of data at http://www.cypress.com /internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ). cortex \ m3 dma scan ? jtag address ? decoder bus ? arb trap ? & ? patch ahb2apb wd ? timer remap ? & ? pause 32 \ bit ? apb 32 \ bit ? ahb ahb2mem ahb2ebi external ? bus ? i/f rom ahb2mem ram pmu ? control uart debug ? uart ptu i/o ? port ? control pmu lpo por buffer apu bt ? clk/ hopper blue ? rf ? i/f rx/tx buffer digital ? modulator calibration ? & ? control digital ? demod ? bit ? sync bluetooth ? radio rf flash ? i/f jtag digital ? i/o i2c_master interrupt ? controller pcm gpio+aux sw ? timers jtag ? master lcu spi ? master low ? power ? scan blue ? rf ? registers adc mic
document number: 002-14874 rev. *s page 3 of 51 cyw20734 contents 1. functional description ................................................. 4 1.1 bluetooth baseband core ..................................... 4 1.2 microprocessor unit .............................................. 5 1.3 integrated radio transceiver ................................ 6 1.4 peripheral transport unit ...................................... 8 1.5 pcm interface ..................................................... 10 1.6 clock frequencies ............................................... 10 1.7 gpio ports .......................................................... 12 1.8 keyboard scanner ............................................... 12 1.9 mouse quadrature signal decoder ..................... 13 1.10 adc port ........................................................... 13 1.11 microphone input ......... .............. .............. .......... 13 1.12 pwm.................................................................. 14 1.13 shutter control for 3d glasses ......................... 15 1.14 triac control ................ ...................................... 15 1.15 serial peripheral interf ace ................................. 15 1.16 infrared modulator ............................................. 15 1.17 infrared learning ............................................... 16 1.18 power management unit.. ............... .............. .... 16 2. pin assignments ........................................................ 17 2.1 pin descriptions .................................................. 17 2.2 ball map .............................................................. 24 3. specifications ............................................................. 25 3.1 electrical characteristics ..................................... 25 3.2 rf specifications ................................................ 30 3.3 timing and ac characteri stics............................ 33 4. mechanical information ............................................. 44 4.1 package diagram ................................................ 44 4.2 tape reel and packaging specifications ............ 45 5. ordering information .................................................. 46 document history .......................................................... 48
document number: 002-14874 rev. *s page 4 of 51 cyw20734 1. functional description 1.1 bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time-c ritical functions required for hi gh-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of dat a for all connections. it also buffers data that passes through it, handles data flow control, schedules sco/ac l and tx/rx transactions, monitors bluetoo th slot usage, optimally segments and packages data into baseband packets, manages connection status i ndicators, and composes and decodes hci packets. in addition to these functions, it independently hand les hci event types, and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data before sending over the air: symbol timing recovery, data deframing, forward error correct ion (fec), header error control (hec), cyclic redundancy check (crc), data decryption, and data dewhitening in the receiver. data framing, fec generation, hec generat ion, crc generation, key generation, data encryption, and data whitening in the transmitter. 1.1.1 bluetooth 4.0 features the bbc supports all bluetooth 4.0 fe atures, with the following benefits: dual-mode bluetooth low energy (bt and ble operation). extended inquiry response (eir): shortens the time to retr ieve the device name, specif ic profile, and operating mode. encryption pause resume (epr): enables the use of bluet ooth technology in a much more secure environment. sniff subrating (ssr): optimizes power consumption for low duty cycle asymmetric data flow, wh ich subsequently extends battery life. secure simple pairing (ssp): reduces the num ber of steps for conn ecting two devices, wi th minimal or no us er interaction requir ed. link supervision time out (lsto): additional commands added to hci and link management protocol (lmp) for improved link time-out supervision. quality of service (qos) enhancements: changes to data traffic control, which results in better link performance. audio, human interface device (hid), bulk traffic, sco, and enhanced sco (e sco) are improved with the erroneous data (ed) and packet boundary flag (pbf) enhancements. 1.1.2 bluetooth 4.1 features the cyw20734 supports the following bluetooth v4.1 features. secure connections (br/edr) fast advertising interval piconet clock adjust connectionless broadcast le privacy v1.1 low duty cycle directed advertising le dual mode topology
document number: 002-14874 rev. *s page 5 of 51 cyw20734 1.1.3 link control layer the link control layer is part of the bluetooth link control func tions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command contro ller that takes commands from the software, and other controllers that are activated o r configured by the command controller, to perform th e link control tasks. each task is perfor med in a different state or substat e in the bluetooth link controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff 1.1.4 test mode support the cyw20734 fully supports bluet ooth test mode as described in part i:1 of the specification of the bluetooth system version 3 .0. this includes the transmitter tests, normal and del ayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the cyw20734 also supports enhanced testing features to simplify rf debugging and qualification and type-approval testing. these features include: fixed frequency carrier wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis fixed frequency constant receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissi ons testing for receive mode fixed frequency constant transmission ? 8-bit fixed pattern or prbs-9 ? enables modulated signal measurements with standard rf test equipment 1.1.5 frequency hopping generator the frequency hopping sequence generator selects the correct hopping channel number based on the li nk controller state, bluetoo th clock, and device address. 1.2 microprocessor unit the cyw20734 microprocessor unit runs software from the link contro l (lc) layer up to the host c ontroller interface (hci). the microprocessor is based on the cortex-m3 32-bit risc proce ssor with embedded ice-rt debug an d jtag interface units. the microprocessor also includes 848 kb of rom memory for program storage and boot rom, 352 kb of ram for data scratch-pad, and patch ram code. the internal boot rom provides flexibility during power-on reset to enable the same device to be used in various configurations . at power-up, the lower layer protocol stack is executed from the internal rom. external patches can be applied to the rom-based firmware to pr ovide flexibility for bug fixes and features additions. these pa tches can be downloaded using external nvram. the device can also suppor t the integration of user applications and profiles using an external serial flash memory.
document number: 002-14874 rev. *s page 6 of 51 cyw20734 1.2.1 nvram configuration data and storage nvram contains configuration information about th e customer application, including the following: fractional-n information bd_addr uart baud rate sdp service record file system information used fo r code, code patches, or data. the cyw20734 can use spi flash or i 2 c eeproms for nvram storage. 1.2.2 external reset an external active-low reset si gnal, reset_n, can be us ed to put the cyw20734 in the reset state. an ex ternal voltage detector reset ic with 50 ms delay is needed on the reset_n. the reset_n should be released only after the vddo supply voltage level has been stabilized for 50 ms. figure 2. reset timing 1.3 integrated radio transceiver the cyw20734 has an integrated radio transce iver that has been optimized for use in 2.4 ghz bluetoot h wireless systems. it has been designed to provide low-power, low-cost, robust communicati ons for applications operating in the globally available 2.4 ghz unlicensed ism band. the cyw20734 is fully compliant with th e bluetooth radio specificatio n and enhanced data rate (edr) specification and meets or exceeds the requirements to provide the highest communication link quality of service. vddio por vddio reset (external) vddc 50 ms vddc reset (internal) xtal_reset xtal_buf_pu ~2.4 ms 0.5 ms ~2.4 ms 10 lpo cycles 8 lpo cycles
document number: 002-14874 rev. *s page 7 of 51 cyw20734 1.3.1 transmit the cyw20734 features a fully integrated ze ro-if transmitter. the baseband transmit da ta is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path consists of signal filtering, i/q upconve rsion, output power amplifier, and rf filtering. the transmitter path also incorporates ? /4-dqpsk for 2 mbps and 8-dpsk for 3 mbps to support edr. the transmitter section is compatible to the bluetoot h low energy specification. the transmitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. 1.3.2 digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4-dqpsk, and 8-dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the trans- mitted signal and is much more stable than direct vco modulation schemes. 1.3.3 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit- synchronization algorithm. 1.3.4 power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature-compensated design. this prov ides greater flexibility in front-end matching and filtering. due to th e linear nature of the pa combi ned with some integrated filte ring, external filtering is required to meet the bluetooth and regulatory harmonic and spurious requirements. for integrated mobile handset ap pli- cations in which bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. the transmitter featur es a sophisticated on-chip transm it signal strength indicator (tssi) block to keep the absolute output power variation withi n a tight range across process, voltage, and temperature. 1.3.5 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz is m band. the front-end topology, with built-in out-of-band attenua tion, enables the cyw20734 to be used in most appl ications with minimal off-chip filtering. for integrated handset operation, in whic h the bluetooth function is integrated close to the cellular transmitter, external filtering is requir ed to eliminate the desensitiza tion of the receiver by the cellular transmit signal. 1.3.6 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. 1.3.7 receiver signal strength indicator the radio portion of the cyw20734 provides a receiver signal strength indicator (rssi) signal to the baseband, so that the cont roller can take part in a bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine wheth er the transmitter should increase or decrease its output power. 1.3.8 local oscillator generation a local oscillator (lo) generation provides fast frequency hoppi ng (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immu nity to lo pulling during pa operation. the cyw20734 uses an internal rf and if loop filter. 1.3.9 calibration the cyw20734 radio transceiver features an aut omated calibration scheme that is fully self-contained in the radio. no user inte raction is required during normal operation or during manufacturing to provide optimal performa nce. calibration tunes the performance o f all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matc hing between key components, and key gain blocks. this takes in to account process variation and te mperature variation. calibration o ccurs transparently during normal operation during the settling time of the hops, and calibrat es for temperature variations as the de vice cools and heats during normal o peration in its environment. 1.3.10 internal ldo the cyw20734 has a 1.2v internal ldo that supplies power to the baseband and the radio.
document number: 002-14874 rev. *s page 8 of 51 cyw20734 1.4 peripheral transport unit 1.4.1 broadcom serial communications interface the cyw20734 provides a 2-pin master bsc interface, which can be used to retrieve configuration information from an external eeprom or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ics used in mouse devices. the bsc interface is compatible with i 2 c slave devices. bsc does not support multimaster capability or flexible wait-state insertion by either master or slave devices. the following transfer clock rates are supported by bsc: 100 khz 400 khz 800 khz (not a standard i 2 c-compatible speed.) 1 mhz (compatibility with high-speed i 2 c-compatible devices is not guaranteed.) the following transfer types are supported by bsc: read (up to 127 bytes can be read.) write (up to 127 bytes can be written.) read-then-write (up to 127 bytes can be read and up to 127 bytes can be written.) write-then-read (up to 127 bytes can be writ ten and up to 127 bytes can be read.) hardware controls the transfers, requiring minimal firmware setup and supervision. the clock pin (scl) and data pin (sda) are both open-drain i/o pins. pull -up resistors external to the cyw20734 are required on both the scl and sda pins for proper operation. 1.4.2 uart interface the uart physical interface is a standard, 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 6 mbps. during initial boot, uart speeds may be limited to 750 kbps. the baud rate may be selected via a vendor-specific uart hci command. the cyw20734 has a 1040-byte receive fifo and a 1 040-byte transmit fifo to support enhanced data rates. the interface supports the bluetooth uart hci (h4) specification. the default baud rate for h4 is 115.2 kbaud. the uart clock default setting is 24 mhz, and can be configured to run as high as 48 mhz to support up to 6 mbps. the baud rate of the cyw20734 uart is controlled by two values. the first is a uart clock divisor (set in the dlbr register) that divides the uart clock by an integer multiple of 16. the second is a baud rate adj ustment (set in the dhbr register ) that is used to specify a n umber of uart clock cycles to stuff in the first or second half of each bit time. up to eight uart cycles can be inserted into the fi rst half of each bit time, and up to eight uart clock cycles can be inserted into the end of each bit time. ta b l e 2 contains example values to generate common baud rates with a 24 mhz uart clock. table 2. common baud rate examples, 24 mhz clock baud rate (bps) baud rate adjustment mode error (%) high nibble low nibble 3m 0xff 0xf8 high rate 0.00 2m 0xff 0xf4 high rate 0.00 1m 0x44 0xff normal 0.00 921600 0x05 0x05 normal 0.16 460800 0x02 0x02 normal 0.16 230400 0x04 0x04 normal 0.16 115200 0x00 0x00 normal 0.16 57600 0x00 0x00 normal 0.16 38400 0x01 0x00 normal 0.00 28800 0x00 0x00 normal 0.16 19200 0x01 0x01 normal 0.00 14400 0x00 0x00 normal 0.16 9600 0x02 0x02 normal 0.00
document number: 002-14874 rev. *s page 9 of 51 cyw20734 ta b l e 3 contains example values to generate common baud rates with a 48 mhz uart clock. normally, the uart baud rate is set by a configuration record downloaded after reset. support for changing the baud rate during normal hci uart operation is included through a vendor-specific co mmand that allows the host to adjust the contents of the baud rate registers. the cyw20734 uart operates correctly with the host uart as long as the combined baud rate error of the two devices is within 2.5%. this should include all temperature, voltage, and process variation dependent offsets. 1.4.3 peripheral uart interface the cyw20734 has a second uart that may be used to interface to other peripherals. this peripheral uart is accessed through the optional i/o ports, which can be conf igured individually and separately for each functional pin as shown in table 4 . table 3. common baud rate examples, 48 mhz clock baud rate (bps) high rate low rate mode error (%) 6m 0xff 0xf8 high rate 0 4m 0xff 0xf4 high rate 0 3m 0x0 0xff normal 0 2m 0x44 0xff normal 0 1.5m 0x0 0xfe normal 0 1m 0x0 0xfd normal 0 921600 0x22 0xfd normal 0.16 230400 0x0 0xf3 normal 0.16 115200 0x1 0xe6 normal ?0.08 57600 0x1 0xcc normal 0.04 38400 0x11 0xb2 normal 0 19200 0x22 0x64 normal 0 table 4. cyw20734 peripheral uart pin name puart_tx puart_rx puart_cts_n puart_rts_n configured pin name p0 p2 p3 p1 p5 p4 p7 p6 p24 p25 p35 p30 p31 p33 ? ? p32 p34 ? ?
document number: 002-14874 rev. *s page 10 of 51 cyw20734 1.5 pcm interface the cyw20734 includes a pcm interfac e that shares pins with the i 2 s interface. the pcm interfac e on the cyw20734 can connect to linear pcm codec devices in master or slave mode. in master mode, the cyw20734 generates the pcm_clk and pcm_sync signals. in slave mode, these signals are provided by another master on the pcm in terface and are inputs to the cyw20734. the configuration of the pcm interface may be adjusted by the host through the use of vendor-specific hci commands. 1.5.1 slot mapping the cyw20734 supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by us ing a time-slotting scheme where the 8 khz or 16 khz audio sam ple interval is divided into as many as 16 slots. the number of sl ots is dependent on the selected interface rate (128 khz, 512 khz , or 1024 khz). the corresponding number of slots for these interface ra te is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. t he pcm data output driver tristate s its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its ou tput after the falling edge of th e pcm clock during the last bit of the slot. 1.5.2 frame synchronization the cyw20734 supports both short- and long- frame synchronization in both master and slave modes. in short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slave looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at th e next rising edge of the cl ock. in long-frame synchroni zation mode, the frame synchr onization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts c oincident with the first bit of the first slot. 1.5.3 data formatting the cyw20734 may be configured to generate and accept several different data formats. for conventional narrowband speech mode, the cyw20734 uses 13 of the 16 bits in each pcm frame. the location and order of thes e 13 bits can be configured to support var ious data formats on the pcm interface. the remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. the default format is 13-bit 2? s complement data, left justified, and clocked msb first. 1.5.4 burst pcm mode in this mode of operation, the pcm bus runs at a significantly higher rate of operati on to allow the host to duty cycle its ope ration and save current. in this mode of operation, the pcm bus can operate at a rate of up to 24 mhz. this mode of operation is initiated with an hci command from the host. 1.6 clock frequencies the cyw20734 uses a 24 mhz crystal oscillator (xtal). 1.6.1 crystal oscillator the xtal must have an accuracy of 20 ppm as defined by the blue tooth specification. two external load capacitors in the range of 5 pf to 30 pf are required to work with the crystal oscillat or. the selection of the load c apacitors is xtal-dependent (see figure 3 ). figure 3. recommended oscillator configuration?12 pf load crystal 22 ? pf 20 ? pf crystal xin xout
document number: 002-14874 rev. *s page 11 of 51 cyw20734 ta b l e 5 ? shows ? the ? recommended ? crystal ? specifications. 1.6.2 hid peripheral block the peripheral blocks of the cyw20734 all r un from a single 128 khz low-power rc oscillator. the oscillator can be turned on at the request of any of the peripherals. if the peripheral is not enabled, it shall not assert its clock request line. the keyboard scanner is a special case, in that it may drop it s clock request line even when enabled, and then reassert the clo ck request line if a keypress is detected. 1.6.3 32 khz crystal oscillator figure 4 shows the 32 khz xtal oscillator with external components and table 6 lists the oscillator?s characteristics. it is a standard pierce oscillator using a comparator with hysteresis on the out put to create a single-ended digita l output. the hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mv. this circuit can be operated with a 32 khz or 32.768 khz crystal oscillator or be driven with a cl ock input at similar frequency. the default component values ar e: r1 = 10 m ? and c1 = c2 = ~10 pf. the values of c1 and c2 are used to fine-tune the oscillator. figure 4. 32 khz osci llator block diagram table 5. reference crystal electrical specifications parameter conditions minimum typical maximum unit nominal frequency ? ? 24.000 ? mhz oscillation mode ? fundamental ? frequency tolerance @25c ? 10 ? ppm tolerance stability over temp @0c to +70c ? 10 ? ppm equivalent series resistance ? ? ? 50 ? load capacitance ? ? 12 ? pf operating temperature range ? 0 ? +70 c storage temperature range ? ?40 ? +125 c drive level ? ? ? 200 w aging ? ? ? 10 ppm/year shunt capacitance ? ? ? 2 pf c2 c1 r1 32.768 ? khz xtal
document number: 002-14874 rev. *s page 12 of 51 cyw20734 1.7 gpio ports the cyw20734 has 40 general-purpose i/os (gpios) in a 90-pin pa ckage. all gpios support programmable pull-ups and are capable of driving up to 8 ma at 3.3v or 4 ma at 1.8v, except p26, p27, p28, and p29, which are capable of driving up to 16 ma at 3.3v o r 8 ma at 1.8v. port 0?port 1, port 8?port 19, po rt 21?port 23, and port 28?port 38 all of these pins can be programmed as adc inputs. port 26?port 29 p[26:29] consist of four pins. all pins are capable of sinking up to 16 ma for leds. these pins also have the pwm function, whic h can be used for led dimming. 1.8 keyboard scanner the keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host microcontroller to intervene. the scanner has the following features: ability to turn off its cl ock if no keys are pressed. sequential scanning of up to 160 keys in an 8 20 matrix. programmable number of columns from 1 to 20. programmable number of rows from 1 to 8. 16-byte key-code buffer (can be augmented by firmware). 128 khz clock that allows scanning of full 160-key matrix in about 1.2 ms. n-key rollover with selective 2-key lockout if ghost is detected. keys are buffered until host microcontroller has a ch ance to read it, or until overflow occurs. hardware debouncing and noise/glitch filtering. low-power consumption. single-digit a-level sleep current. 1.8.1 theory of operation the key scan block is controlled by a st ate machine with the following states: 1.8.2 idle the state machine begins in the idle state. in this state, all column outputs are driven high. if any key is pressed, a transit ion occurs on one of the row inputs. this transition causes the 128 khz cl ock to be enabled (if it is not already enabled by another perip heral) and the state machine to enter the scan state. also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0. table 6. xtal oscillator characteristics parameter symbol conditions minimum typical maximum unit output frequency f oscout ? ? 32.768 ? khz frequency tolerance ? crystal-dependent ? 100 ? ppm start-up time t startup ???500ms xtal drive level p drv for crystal selection 0.5 ? ? w xtal series resistance r series for crystal selection ? ? 70 k ? xtal shunt capacitance c shunt for crystal selection ? ? 1.3 pf
document number: 002-14874 rev. *s page 13 of 51 cyw20734 1.8.3 scan in the scan state, a row counter counts from 0 up to a programmabl e number of rows minus 1. after the last row is reached, the row counter is reset and the column counter is incremented. this cycle repeats until the row and co lumn counters are both at their respective terminal count values. at that point, the state machine moves into the scan-end state. as the keys are being scanned, the key-index counter is incremented. this counter value is compared to the modifier key codes s tored in ram, or in the key-code buffer if the key is not a modifier key. it can be used by the microprocessor as an index into a loo kup table of usage codes. also, as the n th row is scanned, the row-hit register is ored with the current 8-bit row input valu es if the current column contains two or more row hits. during the scan of any column, if a key is det ected at the current row, and the row-hit register indicates th at a hit was detected in that same row on a previous column, then a ghos t condition may have occurred, and a bit in the status register is set to indicate this. 1.8.4 scan end this state determines whether any keys were detected while in the scan state. if yes, the state machine returns to the scan sta te. if no, the state machine returns to the idle state, an d the 128 khz clock request signal is made inactive. note: the microcontroller can poll the key status register. 1.9 mouse quadrature signal decoder the mouse signal decoder is designed to autonomously sample two quadr ature signals commonly generated by an optomechanical mouse. the decoder has the following features: three pairs of inputs for x, y, and z (typical scr oll wheel) axis signals. each axis has two options: ? for the x axis, choose p2 or p32 as x0 and p3 or p33 as x1. ? for the y axis, choose p4 or p34 as y0 and p5 or p35 as y1. ? for the z axis, choose p6 or p36 as z0 and p7 or p37 as z1. control of up to four external high-curre nt gpios to power external optoelectronics: ? turn-on and turn-off time can be staggered for each hc-gpio to avoid simultaneous switching of hi gh currents and having multipl e high-current devices on at the same time. ? sample time can be staggered for each axis. ? sense of the control signal can be active high or active low. ? control signal can be tristated for off condition or driven high or low, as appropriate. 1.9.1 theory of operation the mouse decoder block has four 10-bit pwms for controlling ex ternal quadrature devices and sampling the quadrature inputs at its core. the gpio signals may be used to control such items as leds, ex ternal ics that may emulate quadr ature signals, photodiodes, and photodetectors. 1.10 adc port the adc block is a single switched-cap - ? adc core for audio and dc measurement. it operates at the 12 mhz clock rate and has 32 dc input channels, including 28 gpio inputs. the internal bandgap reference has 5% accuracy without calibration. different calibration and digital correction schemes can be applied to r educe adc absolute error and improve measurement accuracy in dc mode. 1.11 microphone input the cyw20734 integrates support for a differential or single-e nded mono microphone. this reduces the requirement on external components because there is no need for a separate microphone amplifier. the microphone input has a user-programmable gain range of 0?42 db with 3 db steps. a microphon e bias output from the chip is provided th at can be used to bias an electret conden ser- type microphone. the mic bias reference outpu t voltage is 2.1v or 21/25 of the audi o power supply. the mic block can be powered down when it is not in use.
document number: 002-14874 rev. *s page 14 of 51 cyw20734 1.12 pwm the cyw20734 has four internal pwms. the pwm module consists of the following: pwm1?4 each of the four pwm channels, pwm1?4, contains the following registers: ? 10-bit initial value register (read/write) ? 10-bit toggle register (read/write) ? 10-bit pwm counter value register (read) pwm configuration register shared among pwm1?4 (read/write). this 12-bit register is used: ? to configure each pwm channel ? to select the clock of each pwm channel ? to change the phase of each pwm channel figure 5 shows the structure of one pwm. figure 5. pwm block diagram pwm_cfg_adr ? register pwm#_init_val_adr ? register pwm#_togg_val_adr ? register pwm#_cntr_adr enable cntr ? value ? is ? arm ? readable clk_sel o_flip 10'h000 10'h3ff 10 10 10 example: ? pwm ? cntr ? w/ ? pwm#_init_val ? = ? 0 ? (dashed ? line) pwm ? cntr ? w/ ? pwm#_init_val ? = ? x ? (solid ? line) ?????????????????? 10'hx pwm_out pwm_togg_val_adr pwm_out
document number: 002-14874 rev. *s page 15 of 51 cyw20734 1.13 shutter control for 3d glasses the cyw20734, combined with the cypress bluetooth host device, provides full system support for 3d glasses on televisions. the cypress bluetooth host device gets frame synchronization signals from the tv, converts them in to proprietary timing control messages, then passes the messages to the cyw20734. the cyw 20734 uses these messages to synchronize the shutter control for the 3d glasses with the television frames. the cyw20734 can provide up to four synchroni zed control signals for left and right eye shutter control. these four lines can o utput pulses with microsecond resolution for on and off timing. t he total cycle time can be set for any period up to 65535 msec. the pulses are synchronized to each other for left and right eye shutters. the cyw20734 seamlessly adjusts the timing of the control signals based on control messages from the cypress bluetooth host device, ensuring that the 3d glasses remain synchroniz ed to the tv display frame. 3d hardware control on the cyw20734 works independently of th e rest of the system. the cyw 20734 negotiates sniff with the cypress bluetooth host device and, except for sniff resynchroniza tion periods, most of the cyw20734 circuitry remains in a low power state while the 3d glasses subsystem continues to provide shutte r timing and control pulses. this significantly reduces total s ystem power consumption. 1.14 triac control the cyw20734 includes hardware support for zero-crossing detection and trigger control for up to four triacs. the cyw20734 dete cts zero-crossing on the ac zero detection line and uses that to prov ide a pulse that is offset from the zero crossing. this allows the cyw20734 to be used in dimmer applications, as well as any other applications that require a cont rol signal that is offset from an input event. the zero-crossing hardware includes an option to suppress glitches. 1.15 serial pe ripheral interface the cyw20734 has two independent spi interfac es. one is a master-only interface (spi_2 ) and the other (spi_1) can be either a master or a slave. each interface has a 64-byte transmit buffer and a 64-byte receive buffer. to support more flexibility for u ser applications, the cyw20734 has optional i/o ports that can be conf igured individually and separately for each functional pin. t he cyw20734 acts as an spi master device that supports 1.8v or 3.3v spi slaves. the cyw20734 can also act as an spi slave device that supports a 1.8v or 3.3v spi master. note : spi voltage depends on vddo/vddm; therefore, it def ines the type of devices that can be supported. 1.16 infrared modulator the cyw20734 includes hardware support for infrared tx. the ha rdware can transmit both modulated and unmodulated waveforms. for modulated waveforms, hardware inserts the desired carrier frequency into all ir transmissions. ir tx can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral uart transmitter. if descriptors are used, they include ir on/off state and the du ration between 1?32767 sec. the cyw20734 ir tx firmware driver inserts this information in a hardware fifo and makes sure that all descriptors are played out without a glitch due to underrun (see figure 6 ). figure 6. infrared tx
document number: 002-14874 rev. *s page 16 of 51 cyw20734 1.17 infrared learning the cyw20734 includes hardware support for infrared learning. th e hardware can detect both modulated and unmodulated signals. for modulated signals, the cyw20734 can dete ct carrier frequencies between 10 khz and 50 0 khz, and the duration that the signal is present or absent. the cyw20734 firmware driver supports furt her analysis and compression of the learned signal. the learned signal can then be played back through the cyw20734 ir tx subsystem (see figure 7 ). figure 7. infrared rx 1.18 power management unit the power management unit (pmu) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. 1.18.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans- ceiver, which then processes the power-down functions accordingly. 1.18.2 host controller power management power is automatically managed by the firmware based on input dev ice activity. as a power-saving task, the firmware controls th e disabling of the on-chip regulator when in hidoff (deep sleep) mode. 1.18.3 bbc power management there are several low-power operations for the bbc: physical layer packet handling turns rf on and off dynamically within packet tx and rx. bluetooth-specified low-power connection mode. while in these low-power connecti on modes, the cyw20734 runs on the low power oscillator and wakes up after a predefined time period. the cyw20734 automatically adjusts its pow er dissipation based on user activity. the following power modes are supported: active mode idle mode sleep mode hidoff (deep sleep) mode the cyw20734 transitions to the next lower state after a programmabl e period of user inactivity. when user activity resumes, th e cyw20734 immediately enters active mode. in hidoff mode, the cyw20734 baseband and core are powered off by disabling power to vddc_out and pavdd. the vddo domain remains powered up and will turn the remainder of the chip on when it detects user events. this mode minimizes chip powe r consumption and is intended fo r long periods of inactivity.
document number: 002-14874 rev. *s page 17 of 51 cyw20734 2. pin assignments 2.1 pin descriptions table 7. pin descriptions pin number pin name i/o power domain description radio i/o a1 rfop i/o pavdd rf antenna port rf power supplies d1 ifvdd1p2 i ifvdd1p2 ifpll power supply b1 lnavdd1p2 i lnavdd1p2 rf front-end supply c1 vcovdd1p2 i vcovdd1p2 vco supply b2 pllvdd1p2 i pllvdd1p2 rfpll and crystal oscillator supply a3 pavdd o pavdd pa supply power supplies f1, g3 vddc i vddc baseband core supply a9, k1 vddo i vddo i/o pad and core supply b6 mic_avdd i mic_avdd microphone supply a5 adc_avbat i adc_avbat adc supply a8 adc_avddc i adc_avddc adc supply ground a2, a10, b5, c2, c3, d3, f2, j1, k10 vss i vss ground b8 avss i avss analog ground clock generator and crystal interface b4 xtali i pllvdd1p2 crystal oscillator input. see ?crystal oscillator? on page 10 for options. a4 xtalo o pllvdd1p2 crystal oscillator output. e6 xtali32k i pllvdd1p2 low-power oscillator input. f6 xtalo32k o pllvdd1p2 low-power oscillator output. core h3 reset_n i/o pu vddo active-low system rese t with open-drain output and internal pull-up resistor. f5 tm1 i vddo device test mode control. connect to gnd for all applications. e5 jtag_sel i vddo arm jtag debug mode control. connect to gnd for all applications. microphone a7 micp i mic_avdd microphone positive input b7 micn i mic_avdd microphone negative input a6 mic_bias o mic_avdd microphone bias supply pcm2/i 2 s j3 pcm_sync i/o, pd vddo frame synch ronization for pcm interface. alternate function: i 2 s word select k2 pcm_clk i/o, pd vddo clock for pcm interface. alternate function: i 2 s clock
document number: 002-14874 rev. *s page 18 of 51 cyw20734 k3 pcm_in i, pu vddo data in put for pcm interface. alternate function: i 2 s data input sda j2 pcm_out o, pd vddo data output for pcm interface. alternate function: i 2 s data output scl uart h5 uart_rxd i vddo uart serial input ? serial data input for the hci uart interface. h4 uart_txd o, pu vddo uart serial output ? serial data output for the hci uart interface. j4 uart_rts_n o, pu vddo request to send (rts) for hci uart interface. leave unconnected if not used. j5 uart_cts_n i, pu vddo clear to send (cts) for hci uart interface. leave uncon- nected if not used. bsc/spi h1 spi_miso_scl i/o vddo bsc clock g1 spi_mosi_sda i/o vddo bsc data g2 spi_clk i/o vddo serial flash spi clock h2 spi_csn i/o vddo serial flas h active-low chip select ldo regulator power supplies b3 vbat i vbat 1.2v ldo input e1 vddc_out o vddc_out 1.2v ldo output reserved f4 reserved0 i vddo reserved. leave unconnected. d5 reserved1 i vddo reserved. leave unconnected. e3 reserved2 i vddo reserved. connect to gnd. e4 reserved3 i vddo reserved. leave unconnected. d4 reserved4 i vddo reserved. connect to gnd. table 7. pin descriptions (cont.) pin number pin name i/o power domain description
document number: 002-14874 rev. *s page 19 of 51 cyw20734 table 8. gpio pin descriptions a pin number pin name default di- rection por state post-reset state b power do- main alternate function description g7 p0 input floating floating vddo gpio: p0 keyboard scan input (row): ksi0 a/d converter input 29 peripheral uart: puart_tx spi_1: mosi (master and slave) ir_rx 60hz_main note: not available during tm1 = 1. g6 p1 input floating floating vddo gpio: p1 keyboard scan input (row): ksi1 a/d converter input 28 peripheral uart: puart_rts spi_1: miso (master and slave) ir_tx c9 p2 input floating floating vddo gpio: p2 keyboard scan input (row): ksi2 quadrature: qdx0 peripheral uart: puart_rx spi_1: spi_cs (slave only) spi_1: mosi (master only) e9 p3 input floating floating vddo gpio: p3 keyboard scan input (row): ksi3 quadrature: qdx1 peripheral uart: puart_cts spi_1: spi_clk (master and slave) g10 p4 input floating floating vddo gpio: p4 keyboard scan input (row): ksi4 quadrature: qdy0 peripheral uart: puart_rx spi_1: mosi (master and slave) ir_tx k4 p5 input floating floating vddo gpio: p5 keyboard scan input (row): ksi5 quadrature: qdy1 peripheral uart: puart_tx spi_1: miso (master and slave) bsc: sda
document number: 002-14874 rev. *s page 20 of 51 cyw20734 g4 p6 input floating floating vddo gpio: p6 keyboard scan input (row): ksi6 quadrature: qdz0 peripheral uart: puart_rts spi_1: spi_cs (slave only) 60hz_main b10 p7 input floating floating vddo gpio: p7 keyboard scan input (row): ksi7 quadrature: qdz1 peripheral uart: puart_cts spi_1: spi_clk (master and slave) bsc: scl d7 p8 input floating floating vddo gpio: p8 keyboard scan output (column): kso0 a/d converter input 27 external t/r switch control: ~tx_pd d9 p9 input floating floating vddo gpio: p9 keyboard scan output (column): kso1 a/d converter input 26 external t/r switch control: tx_pd g8 p10 input floating floating vddo gpio: p10 keyboard scan output (column): kso2 a/d converter input 25 external pa ramp control: ~pa_ramp g9 p11 input floating floating vddo gpio: p11 keyboard scan output (column): kso3 a/d converter input 24 c10 p12 input floating floating vddo gpio: p12 keyboard scan output (column): kso4 a/d converter input 23 e8 p13 input floating floating vddo gpio: p13 keyboard scan output (column): kso5 a/d converter input 22 pwm3 triac control 3 table 8. gpio pin descriptions a (cont.) pin number pin name default di- rection por state post-reset state b power do- main alternate function description
document number: 002-14874 rev. *s page 21 of 51 cyw20734 j7 p14 input floating input enable, pull-down vddo gpio: p14 keyboard scan output (column): kso6 a/d converter input 21 pwm2 triac control 4 j8 p15 input floating input enable, pull-up vddo gpio: p15 keyboard scan output (column): kso7 a/d converter input 20 ir_rx 60hz_main b9 p16 input floating floating vddo gpio: p16 keyboard scan output (column): kso8 a/d converter input 19 j10 p17 input floating floating vddo gpio: p17 keyboard scan output (column): kso9 a/d converter input 18 f9 p18 input floating floating vddo gpio: p18 keyboard scan output (column): kso10 a/d converter input 17 h7 p19 input floating floating vddo gpio: p19 keyboard scan output (column): kso11 a/d converter input 16 f10 p20 input floating floating vddo gpio: p20 keyboard scan output (column): kso12 d10 p21 input floating floating vddo gpio: p21 keyboard scan output (column): kso13 a/d converter input 14 triac control 3 e6 p22 input floating floating vddo gpio: p22 keyboard scan output (column): kso14 a/d converter input 13 triac control 4 xtalo32k f6 p23 input floating floating vddo gpio: p23 keyboard scan output (column): kso15 a/d converter input 12 xtali32k table 8. gpio pin descriptions a (cont.) pin number pin name default di- rection por state post-reset state b power do- main alternate function description
document number: 002-14874 rev. *s page 22 of 51 cyw20734 g5 p24 input floating floating vddo gpio: p24 keyboard scan output (column): kso16 spi_1: spi_clk (master and slave) peripheral uart: puart_tx f7 p25 input floating floating vddo gpio: p25 keyboard scan output (column): kso17 spi_1: miso (master and slave) peripheral uart: puart_rx k8 p26 pwm0 input floating input enable, pull-down vddo gpio: p26 keyboard scan output (column): kso18 spi_1: spi_cs (slave only) optical control output: qoc0 triac control 1 current: 16 ma sink k9 p27 pwm1 input floating floating vddo gpio: p27 keyboard scan output (column): kso19 spi_1: mosi (master and slave) optical control output: qoc1 triac control 2 current: 16 ma sink k7 p28 pwm2 input floating input enable, pull-up vddo gpio: p28 optical control output: qoc2 a/d converter input 11 led1 current: 16 ma sink k6 p29 pwm3 input floating floating vddo gpio: p29 optical control output: qoc3 a/d converter input 10 led2 current: 16 ma sink j9 p30 input floating floating vddo gpio: p30 a/d converter input 9 peripheral uart: puart_rts h6 p31 input floating floating vddo gpio: p31 a/d converter input 8 peripheral uart: puart_tx table 8. gpio pin descriptions a (cont.) pin number pin name default di- rection por state post-reset state b power do- main alternate function description
document number: 002-14874 rev. *s page 23 of 51 cyw20734 h9 p32 input floating floating vddo gpio: p32 a/d converter input 7 quadrature: qdx0 spi_1: spi_cs (slave only) auxiliary clock output: aclk0 peripheral uart: puart_tx h10 p33 input floating floating vddo gpio: p33 a/d converter input 6 quadrature: qdx1 spi_1: mosi (slave only) auxiliary clock output: aclk1 peripheral uart: puart_rx h8 p34 input floating floating vddo gpio: p34 a/d converter input 5 quadrature: qdy0 peripheral uart: puart_rx external t/r switch control: tx_pd f8 p35 input floating floating vddo gpio: p35 a/d converter input 4 quadrature: qdy1 peripheral uart: puart_cts bsc: sda d8 p36 input floating floating vddo gpio: p36 a/d converter input 3 quadrature: qdz0 spi_1: spi_clk (master and slave) auxiliary clock output: aclk0 external t/r switch control: ~tx_pd e7 p37 input floating floating vddo gpio: p37 a/d converter input 2 quadrature: qdz1 spi_1: miso (slave only) auxiliary clock output: aclk1 bsc: scl table 8. gpio pin descriptions a (cont.) pin number pin name default di- rection por state post-reset state b power do- main alternate function description
document number: 002-14874 rev. *s page 24 of 51 cyw20734 2.2 ball map the cyw20734 ball map is shown in figure 8 . figure 8. cyw20734 ball map d6 p38 input floating floating vddo gpio: p38 a/d converter input 1 spi_1: mosi (master and slave) ir_tx j6 p39 input floating floating vddo gpio: p39 spi_1: spi_cs (slave only) infrared control: ir_rx external pa ramp control: pa_ramp 60hz_main a. during power-on reset, all inputs are disabled. b. the post-reset state is the gpio state just after a power-on reset before firmware gets loaded. table 8. gpio pin descriptions a (cont.) pin number pin name default di- rection por state post-reset state b power do- main alternate function description 123 45678910 a rfop vss pavdd xtalo adc_ avbat micbias micp adc_ avddc vddo vss a b lnavdd1p2 pllvdd1p2 vbat xtali vss mic_avdd micn avss p16 p7 b c vcovdd1p2 vss vss p2 p12 c d ifvdd1p2 vss reserved4 reserved1 p38 p8 p36 p9 p21 d e vddc_out reserved2 reserved3 jtag_sel p22/ xtali32k p37 p13 p3 e f vddc vss reserved0 tm1 p23/ xtalo32k p25 p35 p18 p20 f g spi_mosi_ sda spi_clk vddc p6 p24 p1 p0 p10 p11 p4 g h spi_miso_ scl spi_csn reset_n uart_txd uart_rxd p31 p19 p34 p32 p33 h j vss pcm_out pcm_sync uart_ rts_n uart_ cts_n p39 p14 p15 p30 p17 j k vddo pcm_clk pcm_in p5 p29 p28 p26 p27 vss k 123 45678910
document number: 002-14874 rev. *s page 25 of 51 cyw20734 3. specifications 3.1 electrical characteristics ta b l e 9 shows the maximum electrical rating for voltages referenced to vdd pin. ta b l e 1 0 shows the power supply characteristics for the range t j = 0c to 125c. table 9. absolute maximum voltages requirement parameter specification unit minimum nominal maximum ambient temperature of operation ?30 25 85 c storage temperature ?40 ? 150 c esd tolerance hbm ?2000 ? 2000 v esd tolerance mm ?100 ? 100 v esd tolerance cdm ?500 ? 500 v latch-up ? 200 ? ma vdd core 1.14 1.2 1.26 v vdd io 1.62 3.3 3.6 v vdd rf (excluding class 1 pa) 1.14 1.2 1.26 v table 10. power supply specifications parameter conditions min. typical max. unit vbat input ? 1.62 3.3 3.6 v operating temperature juncti on temperature ?40 50 125 c total system leakage max value is defined at temp = 85c ?0.51.3 a pmu turn-on time vbat is ready. tbd ? 300 s
document number: 002-14874 rev. *s page 26 of 51 cyw20734 ta b l e 11 ? shows ? the ? digital ? level ? characteristics ? for ? (vss ? = ? 0v). table 11. vddc ldo electrical specifications parameter conditions min. typical max. unit input voltage ? 1.62 3.3 3.6 v nominal output voltage ??1.2v dc accuracy accuracy at any step, including bandgap reference. ?5 ? 5 % output voltage programmability range 0.89 ? 1.34 v step size ? 30 ? mv load current ? ? ? 40 ma dropout voltage i load = 40 ma ? ? 200 mv line regulation vin from 1.62v to 3.6v, i load = 40 ma ? ? 0.2 %vo/v load regulation i load = 1 ma to 40 ma, vout = 1.2v, package + pcb r=0.3 ? ? 0.02 0.05 %vo/ma quiescent current no load @vin = 3.3v ? 18 23 a max load @vin = 3.3v ? ? 0.56 0.65 ma power down current vin = 3.3v @25c ? 0.2 ? a vin = 3.6 @80c ? tbd ? ? output noise i load = 15 ma, 100 khz ? 40 nv/sqrthz i load = 15 ma, 2 mhz ? 14 nv/sqrthz psrr vin = 3.3, vout = 1.2v, i load = 40 ma 1 khz 65 ? ? db 10 khz 60 ? ? db 100 khz 55 ? ? db over current limit ? 100 ? ? ma turn-on time vbat = 3.3v, bg already on, ldo off to on, co = 1 f, 90% of vout ??100 s in-rush current during turn-on during start-up, co = 1 f??60ma transient perfor- mance i load = 1 ma to 15 ma and 15 ma to 1 ma in 1 s ??40mv i load = 15 ma to 40 ma and 40 ma to 15 ma in 1 s ??25? external output capacitor ceramic cap with esr 0.5 ? 0.8 1 4.7 f external input capacitor ceramic, x5r, 0402, 20%, 10v. ? 1 ? f
document number: 002-14874 rev. *s page 27 of 51 cyw20734 table 12. adc microphone specifications parameter symbol conditions/comments min. typical max. unit analog supply voltage avbat battery and i/o supply 1.62 3.3 3.6 v analog core supply avddc 10% 1.08 1.2 1.32 v audio supply mic_avdd only available for audio applications when audio supply is separated from battery supply 1.8 2.5 3.3 v current consumption i tot ??1.2?ma power down current ? ? ? 0.5 ? a adc reference voltage vref from bg with 3% accuracy ? .85 v input clock frequency ? from xtalosc ? 24 26 mhz adc sampling clock ? ? ? 12 mhz absolute error ? includes gain error, offset, and distortion. note : before factory calibration ??5% ? includes gain error, offset, and distortion. note : after factory calibration ??2% effective number of bits (enob) ? for static measurements 10 ? ? bit for audio applications 12 ? ? adc input full scale fs for audio applications ? 1.7 ? vpp for static measurements 1.8 ? 3.6 conversion rate ? for audio applications 16 48 ? khz for static measurements 50 100 ? signal bandwidth ? for audio applications 20 ? 8k hz for static measurements ? dc ? input impedance rin for audio applications 10 ? ? k ? for static measurements 500 ? ? startup time ? for audio applications ? 10 ? ms for static measurements ? 20 ? s mic pga gain range ? ? 0 18 db mic pga gain step ? ? 3 db mic pga gain error ? include part-to-part gain variation ?3 1 3 db pga input reference noise ? @ 18 db pga gain a-weighted ??15v passband gain flatness ? pga + adc 100hz?4khz ?0.5 ? 0.5 db mic bias output voltag e ? @2.5vsupply ? 2.1 ? v mic bias loading current ? ? ? ? 3 ma
document number: 002-14874 rev. *s page 28 of 51 cyw20734 note : in table 13, current consumption measurements are taken at vbat with the assumption that vbat is connected to vddio and ldoin. mic bias noise ? pga input referred. 6 db attenuation is assumed from mic bias output to pga input. 20 hz to 8 khz a-weighted ??3v adc snr ? a-weighted 0 db pga gain 78 ? ? db adc thd + n ? ?3 dbfs input 0 db pga gain 74 ? ? db gpio input voltage ? must be lower than vbat ? ? 3.6 v gpio source impedance a ?resistance ??1k ? ? capacitance ? ? 10 pf a. conditional requirement for the measurement time of 10 s. relaxed with longer meas urement time for each gpio input channel. table 13. digital i/o characteristics characteristics symbol minimum typical maximum unit input low voltage (vddo = 3.3v) v il ??0.8v input high voltage (vddo = 3.3v) v ih 2.0 ? ? v input low voltage (vddo = 1.8v) v il ??0.6v input high voltage (vddo = 1.8v) v ih 1.1 ? ? v output low voltage v ol ??0.4v output high voltage v oh vddo ? 0.4v ? ? v input low current i il ??1.0 a input high current i ih ??1.0 a output low current (vddo = 3.3v, v ol = 0.4v) i ol ??8.0ma output high current (vddo = 3.3v, v oh = 2.9v) i oh ??8.0ma output high current (vddo = 1.8v, v oh = 1.4v) i oh ??4.0ma input capacitance c in ??0.4pf table 12. adc microphone specifications (cont.) parameter symbol conditions/comments min. typical max. unit
document number: 002-14874 rev. *s page 29 of 51 cyw20734 table 14. bluetooth and ble current consumption, class 1 operating mode typical unit dm1/dh1 32.15 ma dm3/dh3 38.14 ma dm5/dh5 38.46 ma 3dh5/3dh5 37.10 ma page scan 486 a sniff slave (495 ms) 254 a sniff slave (22.5 ms) 2.6 ma sniff slave (11.25 ms) 4.95 ma hidoff (deep sleep) 2.69 a ble scan a 355 a ble adv unconnectable 1.00 sec 176 a ble connected 600 ms interval 211 a a. no devices present. a 1.28 second in terval with a scan window of 11.25 ms. table 15. bluetooth and ble current consumption, class 2 (0 dbm) operating mode typical unit dm1/dh1 27.5 ma dm3/dh3 31.34 ma dm5/dh5 32.36 ma 3dh5/3dh5 31.57 ma hidoff (deep sleep) 2.69 a ble scan a a. no devices present. a 1.28 second in terval with a scan window of 11.25 ms. 368 a ble adv unconnectable 1.00 sec 174 a
document number: 002-14874 rev. *s page 30 of 51 cyw20734 3.2 rf specifications note : all specifications in ta b l e 1 6 are for industrial temperatures. all specifications in ta b l e 1 6 are single-ended. unused inputs are left open. table 16. receiver rf specifications parameter conditions minimum typical a maximum unit general frequency range ? 2402 ? 2480 mhz rx sensitivity b gfsk, 0.1% ber, 1 mbps ? ?93.5 ? dbm le gfsk, 0.1% ber, 1 mbps ? ?96.5 ? dbm ? /4-dqpsk, 0.01% ber, 2 mbps ? ?95.5 ? dbm 8-dpsk, 0.01% ber, 3 mbps ? ?89.5 ? dbm maximum input gfsk, 1 mbps ? ? ?20 dbm maximum input ? /4-dqpsk, 8-dpsk, 2/3 mbps ? ? ?20 dbm interference performance c/i cochannel gfsk, 0.1% ber ? 9.5 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ?5 0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ?40 ?30.0 db c/i > 3 mhz adjacent channel gfsk, 0.1% ber ? ?49 ?40.0 db c/i image channel gfsk, 0.1% ber ? ?27 ?9.0 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ?37 ?20.0 db c/i cochannel ? /4-dqpsk, 0.1% ber ? 11 13 db c/i 1 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ?8 0 db c/i 2 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ?40 ?30.0 db c/i > 3 mhz adjacent channel 8-d psk, 0.1% ber ? ?50 ?40.0 db c/i image channel ? /4-dqpsk, 0.1% ber ? ?27 ?7.0 db c/i 1 mhz adjacent to image channel ? /4-dqpsk, 0.1% ber ? ?40 ?20.0 db c/i cochannel 8-dpsk, 0.1% ber ? 17 21 db c/i 1 mhz adjacent channel 8-dpsk, 0.1% ber ? ?5 5 db c/i 2 mhz adjacent channel 8-dpsk, 0.1% ber ? ?40 ?25.0 db c/i > 3 mhz adjacent channel 8-d psk, 0.1% ber ? ?47 ?33.0 db c/i image channel 8-d psk, 0.1% ber ? ?20 0 db c/i 1 mhz adjacent to image chan nel 8-dpsk, 0.1% ber ? ?35 ?13.0 db out-of-band blocking performance (cw) c 30 mhz?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm
document number: 002-14874 rev. *s page 31 of 51 cyw20734 out-of-band blocking perfo rmance, modulated interferer 776?764 mhz cdma ? ?10 d ?dbm 824?849 mhz cdma ? ?10 d ?dbm 1850?1910 mhz cdma ? ?23 d ?dbm 824?849 mhz edge/gsm ? ?10 d ?dbm 880?915 mhz edge/gsm ? ?10 d ?dbm 1710?1785 mhz edge/gsm ? ?23 d ?dbm 1850?1910 mhz edge/gsm ? ?23 d ?dbm 1850?1910 mhz wcdma ? ?23 d ?dbm 1920?1980 mhz wcdma ? ?23 d ?dbm intermodulation performance e bt, df = 5 mhz ? ?39.0 ? ? dbm spurious emissions f 30 mhz to 1 ghz ? ? ? ?62 dbm 1 ghz to 12.75 ghz ? ? ? ?47 dbm 65 mhz to 108 mhz fm rx ? ?147 ? dbm/hz 746 mhz to 764 mhz cdma ? ?147 ? dbm/hz 851?894 mhz cdma ? ?147 ? dbm/hz 925?960 mhz edge/gsm ? ?147 ? dbm/hz 1805?1880 mhz edge/gsm ? ?147 ? dbm/hz 1930?1990 mhz pcs ? ?147 ? dbm/hz 2110?2170 mhz wcdma ? ?147 ? dbm/hz a. typical operating conditions are 1.22v operating voltage and 25c ambient temperature. b. the receiver sensitivity is measured at ber of 0.1% on the device interface. c. meets this specification using front-end band pass filter. d. numbers are referred to the pin output with an external bpf filter. e. f0 = -64 dbm bluetooth-modulated signal, f1 = ?39 dbm sine wave, f2 = ?39 dbm bluetooth-modulated signal, f0 = 2f1 ? f2, and |f2 ? f1| = n*1 mhz, where n is 3, 4, or 5. for the typical case, n = 4. f. includes baseband radiated emissions. table 16. receiver rf specifications (cont.) parameter conditions minimum typical a maximum unit
document number: 002-14874 rev. *s page 32 of 51 cyw20734 note: all specifications in ta b l e 1 7 are for industrial temperatures. all specifications in ta b l e 1 7 are single-ended. unused inputs are left open. table 17. transmitter rf specifications parameter conditions minimum typical maximum unit general frequency range ? 2402 ? 2480 mhz class1: gfsk tx power a a. tbd dbm output for gfsk measured with pavdd = 2.5v. ??12?dbm class1: edr tx power b b. tbd dbm output for edr measured with pavdd = 2.5v. ? ?9?dbm class 2: gfsk tx power ? ? 2 ? dbm power control step ? 2 4 8 db modulation accuracy ? /4-dqpsk frequency stability ? ?10 ? 10 khz ? /4-dqpsk rms devm ? ? ? 20 % ? /4-qpsk peak devm ? ? ? 35 % ? /4-dqpsk 99% devm ? ? ? 30 % 8-dpsk frequency stability ? ?10 ? 10 khz 8-dpsk rms devm ? ? ? 13 % 8-dpsk peak devm ? ? ? 25 % 8-dpsk 99% devm ? ? ? 20 % in-band spurious emissions 1.0 mhz < |m ? n| < 1.5 mhz ? ? ? ?26 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ? ? ?20 dbm |m ? n| > 2.5 mhz ? ? ? ?40 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 c c. maximum value is the value required for bluetooth qualification. dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 c, d d. meets this spec using a front-end band-pass filter. dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm
document number: 002-14874 rev. *s page 33 of 51 cyw20734 3.3 timing and ac characteristics in this section, use th e numbers listed in the reference column of each table to interp ret the following timing diagrams. 3.3.1 uart timing figure 9. uart timing table 18. ble rf specifications parameter conditions minimum typical maximum unit frequency range n/a 2402 ? 2480 mhz rx sense a gfsk, 0.1% ber, 1 mbps ? ?96.5 ? dbm tx power b n/a ?9?dbm mod char: delta f1 average n/a 225 255 275 khz mod char: delta f2 max c n/a 99.9 ? ? % mod char: ratio n/a 0.8 0.95 ? % a. dirty tx is off. b. the ble tx power can be increased to compensate for front-end losses such as bpf, diplexer, switch, etc. the output is capped at 12 dbm out. the ble tx power at the antenna port canno t exceed the 10 dbm eirp specification limit. c. at least 99.9% of all delta f2 max frequency values recorded over 10 packets must be greater than 185 khz. table 19. uart timi ng specifications reference characteristics min. max. unit 1 delay time, uart_cts_n low to uart_txd valid ? 24 baud out cycles 2 setup time, uart_cts_n high bef ore midpoint of stop bit ? 10 ns 3 delay time, midpoint of stop bit to uart_rts_n high ? 2 baud out cycles
document number: 002-14874 rev. *s page 34 of 51 cyw20734 3.3.2 spi timing the spi interface can be clocked up to 24 mhz. ta b l e 2 0 and figure 10 show the timing requirements when operating in spi mode 0 and 2. figure 10. spi timing, mode 0 and 2 table 20. spi mode 0 and 2 reference characteristics minimum maximum unit 1 time from slave assert spi_int to master assert spi_csn (directread) 0 ns 2 time from master assert spi_csn to slave assert spi_int (directwrite) 0 ns 3 time from master assert spi _csn to first clock edge 20 ns 4 setup time for mosi data lines 8 1 / 2 sck ns 5 hold time for mosi data lines 8 1 / 2 sck ns 6 time from last sample on mosi/m iso to slave deassert spi_int 0 100 ns 7 time from slave deassert spi_int to master deassert spi_csn 0 ns 8 idle time between subsequent spi transactions 1 sck ns 5 spi_csn spi_int (directwrite) spi_clk (mode ? 0) spi_mosi \ first ? bit spi_miso not ? driven first ? bit second ? bit second ? bit last ? bit last ? bit 3 4 6 7 8 spi_clk (mode ? 2) spi_int (directread) 1 2 not ? driven \
document number: 002-14874 rev. *s page 35 of 51 cyw20734 ta b l e 2 1 and figure 11 show the timing requirements when operating in spi mode 0 and 2. figure 11. spi timing, mode 1 and 3 table 21. spi mode 1 and 3 reference characteristics minimum maximum unit 1 time from slave assert spi _int to mast er assert spi_csn (directread) 0 ns 2 time from master assert spi_csn to slave assert spi_int (directwrite) 0 ns 3 time from master assert spi_csn to first clock edge 20 ns 4 setup time for mosi data lines 8 1 / 2 sck ns 5 hold time for mosi data lines 8 1 / 2 sck ns 6 time from last sample on mosi/miso to slave deassert spi_int 0 100 ns 7 time from slave deassert spi_int to master deassert spi_csn 0 ns 8 idle time between subsequent spi transactions 1 sck ns 5 spi_csn spi_int (directwrite) spi_clk (mode ? 1) spi_mosi \ invalid ? bit spi_miso not ? driven invalid ? bit first ? bit first ? bit last ? bit last ? bit 3 4 6 7 8 \ not ? driven spi_clk (mode ? 3) spi_int (directread) 1 2
document number: 002-14874 rev. *s page 36 of 51 cyw20734 3.3.3 bsc interface timing the specifications in table 22 references figure 12 . figure 12. bsc interface timing diagram table 22. bsc interface timing specifications (up to 1 mhz) reference characteristics minimum maximum unit 1 clock frequency ? 100 khz 400 800 1000 2 start condition setup time 650 ? ns 3 start condition hold time 280 ? ns 4 clock low time 650 ? ns 5 clock high time 280 ? ns 6 data input hold time a a. as a transmitter, 125 ns of delay is provided to bridge the undefined region of t he falling edge of scl to avoid unintended g eneration of start or stop conditions. 0 ? ns 7 data input setup time 100 ? ns 8 stop condition setup time 280 ? ns 9 output valid from clock ? 400 ns 10 bus free time b b. time that the cbus must be free before a new transaction can start. 650 ? ns 2 8 scl sda in sda out 7 6 1 5 10 3 4 9
document number: 002-14874 rev. *s page 37 of 51 cyw20734 3.3.4 pcm interface timing short frame sync, master mode figure 13. pcm timing diagram (short frame sync, master mode) table 23. pcm interface timing specificat ions (short frame sync, master mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? im pedance 7
document number: 002-14874 rev. *s page 38 of 51 cyw20734 short frame sync, slave mode figure 14. pcm timing diagram (short frame sync, slave mode) table 24. pcm interface timing specifications (short frame sync, slave mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? im pedan ce 8
document number: 002-14874 rev. *s page 39 of 51 cyw20734 long frame sync, master mode figure 15. pcm timing diagram (long frame sync, master mode) table 25. pcm interface timing specificat ions (long frame sync, master mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-14874 rev. *s page 40 of 51 cyw20734 long frame sync, slave mode figure 16. pcm timing diagram (long frame sync, slave mode) table 26. pcm interface timing specifications (long frame sync, slave mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bc lk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-14874 rev. *s page 41 of 51 cyw20734 3.3.5 i 2 s timing the cyw20734 supports two independent i 2 s digital audio ports. the i 2 s interface supports both master and slave modes. the i 2 s signals are: i 2 s clock: i 2 s sck i 2 s word select: i 2 s ws i 2 s data out: i 2 s sdo i 2 s data in: i 2 s sdi i 2 s sck and i 2 s ws become outputs in master mode and inputs in slave mode, while i 2 s sdo always stays as an output. the channel word length is 16 bits and the data is justified so that the msb of the left-channel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the m sb of each data word is transmitt ed one bit clock cycle after the i 2 s ws transition, synchronous with the falling edge of bit clock. left-channel data is transmitted when i 2 s ws is low, and right-channel data is transmitted when i 2 s ws is high. data bits sent by the cyw20734 are synchronized with the falli ng edge of i2s_sck and should be sampled by the receiver on the rising edge of i2s_ssck. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz. note : timing values specified in table 27 are relative to high and low threshold levels.
document number: 002-14874 rev. *s page 42 of 51 cyw20734 note: the time periods specified in figure 17 and figure 18 are defined by the transmitter speed. t he receiver specifications must match transmitter performance. table 27. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min max min max min max min max clock period t t tr ???t r ??? a master mode: clock generated by transmitter or receiver high t hc 0.35t tr ???0.35t tr ??? b lowt lc 0.35t tr ???0.35t tr ??? b slave mode: clock accepted by transmitter or receiver high t hc ?0.35t tr ???0.35t tr ?? c low t lc ?0.35t tr ???0.35t tr ?? c rise time t rc ? ? 0.15t tr ??? ? d transmitter delay t dtr ???0.8t???? e hold time t htr 0??????? d receiver setup time t sr ?????0.2t r ?? f hold time t hr ?????0?? f a. the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. b. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. for thi s reason, t hc and t lc are specified with respect to t. c. in slave mode, the transmitter and receiver need a clock signal wi th minimum high and low periods so that they can detect the signal. so long as the minimum periods are greater than 0.35t r , any clock that meets the requirements can be used. d. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitte r driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefore, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . e. to allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and t, always giving the receiver sufficient setup time. f. the data setup and hold time must not be less t han the specified receiver setup and hold time.
document number: 002-14874 rev. *s page 43 of 51 cyw20734 figure 17. i 2 s transmitter timing figure 18. i 2 s receiver timing sd ? and ? ws sck v l = ? 0.8v t lc >0.35t t rc * t hc >0.35t t v h = ? 2.0v t htr >0 t otr <0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode. sd ? and ? ws sck v l = ? 0.8v t lc >0.35t t hc >0.35 t v h = ? 2.0v t hr >0 t sr >0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document number: 002-14874 rev. *s page 44 of 51 cyw20734 4. mechanical information 4.1 package diagram figure 19. cyw20734 8.5 mm 8.5 mm 90-pin fbga package
document number: 002-14874 rev. *s page 45 of 51 cyw20734 4.2 tape reel and packaging specifications the top-left corner of the cyw20734 package is situated near the sprocket holes, as shown in figure 20 . figure 20. pin 1 orientation table 28. cyw20734 tape reel specifications parameter value quantity per reel 2500 reel diameter 13 inches hub diameter 4 inches tape width 16 mm tape pitch 12 mm pin 1: top left corner of package toward sprocket holes
document number: 002-14874 rev. *s page 46 of 51 cyw20734 5. ordering information table 29. ordering information part number package ambient operating temperature cyw20734ua1kffb3g 90-pin fbga 0c to 70c
document number: 002-14874 rev. *s page 47 of 51 cyw20734 appendix a: acronyms and abbreviations the following list of acronyms and abbrev iations may appear in this document. term description adc analog-to-digital converter afh adaptive frequency hopping ahb advanced high-performance bus apb advanced peripheral bus apu audio processing unit arm7tdmi-s ? acorn risc machine 7 thumb instruction, debugger, multiplier, ice, synthesizable bsc broadcom serial control btc bluetooth controller coex coexistence dfu device firmware update dma direct memory access ebi external bus interface hci host control interface hv high voltage idc initial digital calibration if intermediate frequency irq interrupt request jtag joint test action group lcu link control unit ldo low drop-out lhl lean high land lpo low power oscillator lv logicvision ? mia multiple interface agent pcm pulse code modulation pll phase locked loop pmu power management unit por power-on reset pwm pulse width modulation qd quadrature decoder ram random access memory rc oscillator a resistor-capacitor oscillator is a circuit comp osed of an amplifier, which provides the output signal, and a resistor-capacitor network, which co ntrols the frequency of the signal. rf radio frequency rom read-only memory rx/tx receive, transmit spi serial peripheral interface sw software uart universal asynchronous receiver/transmitter upi -processor interface wd watchdog
document number: 002-14874 rev. *s page 48 of 51 cyw20734 document history document title: cyw20734 single-chip bluetooth transceiver for wireless input devices document number: 002-14874 revision ecn orig. of change submission date description of change ** ? ? 10/28/13 20734-ds100-r initial release. *a ? ? 11/12/13 20734-ds101-r updated: ? the cyw20734 is bluetooth 4.1-compliant. the current version of the cyw20734 does not support hs. ? adaptive frequency hopping is not supported in the current version of the cyw20734. ? ?microprocessor unit? on page 13. ? ?uart interface? on page 17: baud rates up to 6 mbps are now supported. ? table 1: ?common baud rate examples, 24 mhz clock,? on page 18. ? table 12: ?adc microphone specifications,? on page 43. added: ? table 2: ?common baud rate examples, 48 mhz clock,? on page 18. ? table 15: ?current consumption for br and edr, class 1,? on page 46. ? table 16: ?current consumption for br and edr, class 2 (0dbm),? on page 47. *b ? ? 01/27/14 20734-ds102-r updated: ? the cyw20734 now supports generic access profile (gap). ? the cyw0734 now supports a single 1.2v internal ldo. ? cyw20734 package information on page 1. ? ?nvram configuration data and storage? on page 14. ? ?bbc power management? on page 29: vdd2p5_out replaced with pavdd. ? table 6: ?pin descriptions,? on page 30. ? table 7: ?gpio pin descriptions,? on page 32. ? table 9: ?power supply specif ications,? on page 39: removed 2.5v ldo input. ? table 11: ?adc microphone specific ations,? on page 41: effective number of bits. removed ? ?bluetooth low energy? on page 12. ? figure 2: ?ldo functional block,? on page 16. ? ?wideband speech support? on page 20. ? all references to vdd2p5_out were removed. ? table 11: ?btldo_2p5 electric al specifications,? on page 42. *c ? ? 02/25/14 20734-ds103-r updated : ? reserved pins in table 6: ?pin descriptions,? on page 30: changed d3 to e3. ? ?ball maps? on page 38. ? section 4: ?mechanical information,? on page 63. *d ? ? 03/25/14 20734-ds104-r updated: ? table 16: ?receiver rf specifications,? on page 46. ? table 31: ?ordering information,? on page 65 *e ? ? 04/21/14 20734-ds105-r updated: ? table 8: ?absolute maximum voltages,? on page 39 ? table 11: ?adc microphone specifications,? on page 41. ? figure 1: ?functional block diagram,? on page 2 ? table 17: ?transmitter rf specifications,? on page 48 *f ?? 05/19/14 20734-ds106-r updated: ? ?gpio ports? on page 23: replaced ?tbd-pin package? with ?90-pin package.? ? section 5: ?ordering information,? on page 66
document number: 002-14874 rev. *s page 49 of 51 cyw20734 *g ? ? 06/26/14 20734-ds107-r updated: ? ?external reset? on page 14. ? table 12: ?digital i/o characteristics,? on page 42. ? table 14: ?current consumption for br and edr, class 1,? on page 44. ? table 15: ?current consumption for br and edr, class 2 (0 dbm),? on page 45. ? table 16: ?receiver rf specifications,? on page 46. ? table 17: ?transmitter rf specifications,? on page 48. ? ?bsc interface timing? on page 53. ? table 31: ?ordering information,? on page 65. added: ? table 18: ?ble rf specifications,? on page 49. *h ? ? 09/25/14 20734-ds108-r updated: ? table 8: ?absolute maximum voltages,? on page 38. ? table 14: ?current consumption for br and edr, class 1,? on page 42. ? table 15: ?current consumption for br and edr, class 2 (0 dbm),? on page 43. ? table 16: ?receiver rf specifications,? on page 44. ? table 23: ?pcm interface timing specifications (short frame sync, master mode),? on page 52. ? ?pcm interface timing? on page 52. *i ? ? 10/21/14 20734-ds109-r updated: ? ?external reset? on page 13 *j ? ? 12/08/14 20734-ds110-r updated: ? ?external reset? on page 14 ? ?adc port? on page 25 *k ? ? 03/02/15 20734-ds111-r updated: ? table 13: ?bluetooth and ble current consumption, class 1,? on page 44 ? ?bluetooth and ble current consumption, class 2 (0 dbm)? on page 44 *l ? ? 03/02/15 20734-ds112-r updated: ? table 13: ?bluetooth and ble current consumption, class 1,? on page 44 ? ?bluetooth and ble current cons umption, class 2 (0 dbm)? on page 44 *m ? ? 06/26/15 20734-ds113-r updated: ? table 12: ?digital i/o characteristics,? on page 43 *n ? ? 08/17/15 20734-ds114-r updated: ? ?gpio ports? on page 23 ? table 22: ?pcm interface timing specifications (short frame sync, master mode),? on page 53 ? table 23: ?pcm interface timing specifications (short frame sync, slave mode),? on page 54 ? table 24: ?pcm interface timing specifications (long frame sync, master mode),? on page 55 ? table 25: ?pcm interface timing specifications (long frame sync, slave mode),? on page 56 *o ? ? 12/09/15 20734-ds115-r updated: ? table 7: ?gpio pin descriptions,? on page 33 by adding a column for the post-reset state of each gpio *p ? ? 02/09/16 20734-ds116-r updated: ? changed ?spi timing? on page 50 from 12 mhz to 24 mhz document title: cyw20734 single-chip bluetooth transceiver for wireless input devices document number: 002-14874
document number: 002-14874 rev. *s page 50 of 51 cyw20734 *q ? ? 03/15/16 20734-ds117-r updated: ? ?combined baud rate error of the two devices is within 2.5%? *r ? ? 04/25/16 20734-ds118-r deleted: ? ?supports broadcom proprietary le data rate up to 2 mbps?. *s 5452885 utsv 10/04/2016 converted to cypress template document title: cyw20734 single-chip bluetooth transceiver for wireless input devices document number: 002-14874
document number: 002-14874 rev. *s revised october 4, 2016 page 51 of 51 cyw20734 ? cypress semiconductor corporation, 2013-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 51

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